1. Field of the Invention
The present invention relates to an amplification circuit amplifying a pulse signal (e.g., a clock pulse signal), and more particularly to the amplification circuit which will be useful when an oscillation circuit is constituted by combining the amplification circuit with an oscillator (e.g., a quartz oscillator, a ceramic oscillator).
2. Description of the Related Art
A conventional oscillation circuit which is constituted by combining an amplification circuit with an oscillator, is disclosed in, for example, Japanese Laid-Open Patent Publication: HEI02-010869, published on Jan. 16, 1990, and Japanese Laid-Open Patent Publication: HEI05-267935, published on Oct. 15, 1993. Such a conventional oscillation circuit includes a first inverter circuit, a feedback resistor which is parallel connected to the first inverter circuit, a second inverter circuit which adjusts a waveform of an output signal of the first inverter circuit, and an oscillator which is connected in parallel to the first inverter circuit.
The first and second inverters consist of, for example, a complementary MOS circuit (CMOS circuit) which includes a P-channel gate element serially connecting to an N-channel gate element. Such gate elements consist of, for example, a MOS type field effect transistor. The first inverter receives a pulse signal from an oscillator, and compares the received pulse signal with a threshold voltage Vt1 of the first inverter, and then outputs an alternating signal which alternately changes amplitude between plus and minus on the basis of the threshold voltage Vt1. The second inverter compares the alternating signal with a threshold voltage Vt2 of the second inverter and shapes the alternating signal to have a rectangular pulse waveform.
A gate length L and a gate width W of the gate element of the first and second inverters are designed so that the first and second inverters have desired electrical properties. And, a pattern size of the first inverter is different from that of the second inverter. The threshold voltages Vt1 and Vt2 of the first and second inverters are decided on the basis of dimensions of the P type and N type gate elements of the first and second inverters, respectively. Specifically, the threshold voltages Vt1 and Vt2 are decided on the basis of a ratio (a dimension ratio) between the dimension of the P type gate element and that of the N type gate element.
Such dimension is indicated as W/L, whereby L and W denote the gate length and gate width of a transistor, respectively. Similarly, the above mentioned dimension ratio is indicated as Wp/Lp:Wn/Ln, whereby Lp and Wp respectively denote the gate length and gate width of the PMOS transistor, and Ln and Wn respectively denote the gate length and gate width of the NMOS transistor.
In this specification, a MOS transistor is used as the gate element. And, specifically, while the gate length L of the MOS transistor is a length between source and drain regions of the MOS transistor, in this specification, the gate length L of the MOS transistor is explained as a length of a gate electrode along a channel region between the source and drain regions of the MOS transistor.
When the gate element is a MOS transistor having an offset structure, the gate length L of the MOS transistor is equal to a length between source and drain regions of the MOS transistor. And, when the gate element is a MIS transistor, the gate length L of the MIS transistor is equal to a length between source and drain electrodes of the MIS transistor.
When a gap exists or there is a difference between the threshold voltages Vt1 and Vt2 of the first and second inverters, a pulse width of the amplified pulse signal waveform is different from a pulse separation of the amplified pulse signal waveform. As a result, a distortion of the amplified pulse signal occurs. The P type and N type gate elements of the first and second inverters are designed in consideration of the dimensions (Wp/Lp and Wn/Ln) of the gate elements.
However, when the gate electrode of the first inverter extends along a direction which is different from an extending direction of the gate electrode of the second inverter, the gate length and/or the gate width of the gate element of each of the inverters varies, due to expansion and contraction of a semiconductor substrate which occurs because of warping of the semiconductor substrate. Such a variation of one of the inverters in the warp direction of the semiconductor substrate varies the dimensions (Wp/Lp and Wn/Ln). Specifically, since the dimension ratio (Wp/Lp Wn/Ln) of the first and second inverters varies, the threshold voltages Vt1 and Vt2 reciprocally vary. Similarly, such variation also occurs, due to a difference between coefficients of linear thermal expansion of the first and second inverters in response to a crystal orientation of the semiconductor substrate.
And, when the gate length and the gate width of the gate elements of the first inverter are different from those of the second inverter, even if the variation of the dimension of the first inverter is equal to that of the second inverter, the dimension ratio (Wp/Lp:Wn/Ln) between the first and second inverters varies. Such a variation of the dimension ratio (Wp/Lp:Wn/Ln) between the first and second inverters is called to a dimension gap.
The electrical properties of the amplification circuit and the oscillation circuit having the amplification circuit degrades, due to a gap between the threshold voltages Vt1 and Vt2 of the first and second inverters corresponding to the above mentioned dimension gap between the first and second inverters. As a result, the ability of the power supply to provide power without noise is reduced.